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never stop thinking. hy[b/e]25l256160ac hy[b/e]25l256160af 256mbit mobile-ram commercial temperature range extended temperature range data sheet, rev. 1.40, aug. 2005 memory products
edition 2005-08 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. under no circumstances may the infineon technologies produ ct as referred to in this data sheet be used in 1. any applications that are inte nded for military usage (including but not limited to weaponry), or 2. any applications, devices or systems which are safety cr itical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "critical systems"), if a) a failure of the infineon technologies product can re asonable be expected to - directly or indirectly - (i) have a detrimental effect on such critical systems in terms of reli ability, effectivenes s or safety; or (ii) cause the failure of such critical systems; or b) a failure or malfunction of such cr itical systems can reaso nably be expected to - directly or indirectly - (i) endanger the health or the life of the user of such critical systems or any other person; or (ii) otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible).
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram data sheet 3 rev. 1.40, 2005-08 04292004-eqnl-flnw hy[b/e]25l256160ac hy[b/e]25l256160af revision history: rev. 1.40 2005-08 previous revision: rev. 1.30 page subjects (major changes since last revision) all added new product type 9 vdd: editorial change 2 added disclaimer we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram table of contents page data sheet 4 rev. 1.40, 2005-08 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.3 read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.4 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.1 partial array self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.2 temperature compensated self refresh with on-chip temperature sensor . . . . . . . . . . . . . . . . 14 3.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
data sheet 5 rev. 1.40, 2005-08 256mbit mobile-ram mobile-ram hy[b/e]25l256160ac hy[b/e]25l256160af 1overview 1.1 features ?16 mbits 16 organisation ? fully synchronous to positive clock edge ? four internal banks for concurrent operation ? data mask (dm) for byte control with write and read data ? programmable cas latency: 2 or 3 ? programmable burst length: 1, 2, 4, 8, or full page ? programmable wrap sequence: sequential or interleaved ? random column address every clock cycle (1-n rule) ? deep power down mode ? extended mode register for mobile-ram features ? temperature compensated self refresh with on-die temperature sensor ? partial array self refresh ? power down and clock suspend mode ? automatic and controlled precharge command ? auto refresh mode (cbr) ? 8192 refresh cycles / 64 ms ? self-refresh with programmble refresh period ? programmable power reduction feature by pa rtial array activation during self-refresh ? v ddq = 1.8v or 2.5 v or 3.3 v ? v dd = 2.5 v or 3.3 v ? p-tfbga-54 package 9-by-6-ball arra y with 3 depopulated rows (12 x 8 mm 2 ) ? operating temperature range: commercial (0 c to +70 c) extended (?25 c to +85 c) table 1 performance 1) 1) for vddq = 2.5 v or 3.3 v; see table 11 for vddq dependent performance part number speed code ?7.5 unit max. clock frequency @cl3 f ck3 133 mhz min. clock period @cl3 t ck3 7.5 ns min. access time from clock @cl3 t ac3 6.0 ns min. clock period @cl2 t ck2 9.5 ns min. access time from clock @cl2 t ac2 6.0 ns
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram overview data sheet 6 rev. 1.40, 2005-08 1.2 description the 256mbit mobile-ram is a new generation of low power, four bank synchronous dram organized as 4 banks x 4 mbit x 16 with additional features for mobile applications. the synchronous mobile-ram achieves high speed data transfer rates by employing a chip architec ture that prefetches multiple bits and then synchronizes the output data to a system clock. the device adds new features to the industry standards set for synchronous dram products. parts of the memory array can be selected for self-refresh and the refresh period during self-refresh is programmable in 4 steps which drastically reduces the self refresh current, depending on the case temperature of the components in the system application. in addition a ?d eep power down mode? is available. operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate. a sequential and gapless data rate is possible depending on burst length, cas latency and speed grade of the device. the mobile-ram is housed in a fbga ?chip-size? packa ge. the mobile-ram is ava ilable in the commercial (0 c tc 70 c) and extended (?25 c to +85 c) temperature range. table 2 ordering information for non-green products product type 1) function code case temperature range package hyb25l256160ac?7.5 pc133?333?522 commercial (0 c tc 70 c) p-tfbga-54 hye25l256160ac?7.5 pc133?333?522 extended (?25 c to +85 c) p-tfbga-54 table 3 ordering information for green products product type 1) 1) hyb/e: designator for memory components for commercial /extended temperature range 25l: mobile-ram at v dd = 2.5 v 256: 256-mbit density 160: product variation x16 a: die revision a f/c: lead & halogen free / lead-containing ? 7.5: speed grade - see table 1 function code case temperature range package hyb25l256160af?7.5 pc133?333?522 commercial (0 c tc 70 c) p-tfbga-54 hye25l256160af?7.5 pc133?333?522 extended (?25 c to +85 c) p-tfbga-54
data sheet 7 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram pin configuration 2 pin configuration figure 1 pin configuration p-tfbga-54 (16 mb 16) < top-view > 123 789 vss dq15 vssq a vddq dq0 vdd dq14 dq13 vddq b vssq dq2 dq1 dq12 dq11 vssq c vddq dq4 dq3 dq10 dq9 vddq d vssq dq6 dq5 dq8 nc vss e vdd ldqm dq7 udqm clk cke f cas ras we a12 a11 a9 g ba0 ba1 cs a8 a7 a6 h a0 a1 a10/ap vss a5 a4 j a3 a2 vdd
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram pin configuration data sheet 8 rev. 1.40, 2005-08 table 4 input/output signals pin symbol type polarity function f2 clk input positive edge clock the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. f3 cke input active high clock enable cke activates the clk signal when high and deactivates the clk signal when low, thereby initiates eith er the power down mode, suspend mode, or the self refresh mode. g9 cs input active low chip select cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. f8 ras input active low command inputs sampled at the rising edge of the clock, ras , cas , and we (along with cs ) define the command to be executed by the sdram. f7 cas f9 we g8 ba1 input active high bank address inputs ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determine if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. g7 ba0 g1 a12 input active high address inputs during a bank activate command cycle, a12 - a0 define the row address (ra12 - ra0) when sampled at the rising clock edge. during a read or write command cycle, a8-a0 define the column address (ca8 - ca0) when sampled at the rising clock edge. in addition to the column address, a1 0/ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba1, ba0 defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba1 and ba0 to control which bank(s) to precharg e. if ap is high, all four banks will be precharged regardless of the state of ba0 and ba1. if ap is low, then ba1 and ba0 are used to define which bank to precharge. g2 a11 h9 a10/ap g3 a9 h1 a8 h2 a7 h3 a6 j2 a5 j3 a4 j7 a3 j8 a2 h8 a1 h7 a0
data sheet 9 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram pin configuration a2 dq15 input/ output active high data input/output data bus operates in the same manner as on conventional drams. b1 dq14 b2 dq13 c1 dq12 c2 dq11 d1 dq10 d2 dq9 e1 dq8 e9 dq7 d8 dq6 d9 dq5 c8 dq4 c9 dq3 b8 dq2 b9 dq1 a8 dq0 f1 udqm input active high data input/output mask udqm and ldqm are output disable signals during read mode and input mask signals for write data. in read mode, u/ldqm have a latency of two clock cycles and control the output buffers like low active output enable signals. in write mode, u/ldqm have a latency of zero and operate as a word mask by allowing input data to be written if it is low but blocks the write operation if the respective dqm is high. udqm controls the upper byte and ldqm controls the lower byte. e8 ldqm e2 nc ? ? not connected no internal electrical connection is present. a7, b3, c7, d3 v ddq supply ? dq power supply a3 b7 c3 d7 v ssq supply ? dq ground a9 e7 j9 v dd supply ? power supply a1 e3 j1 v ss supply ? ground table 4 input/output signals (cont?d) pin symbol type polarity function
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram pin configuration data sheet 10 rev. 1.40, 2005-08 figure 2 block diagram (16 mbit 16, 13 / 9 / 2 addressing) note: 1. this functional block diagram is inte nded to facilitate user und erstanding of the operatio n of the device; it does not represent an actual circuit implementation. 2. dqm is a unidirectional signal (input only), but is in ternally loaded to match the load of the bidirectional dq signals. memory array bank 1 8192 x 512 x 16 bit memory array bank 2 8192 x 512 x 16 bit memory array bank 3 8192 x 512 x 16 bit spb04124_256m column address counter row decoder memory array bank 0 8192 x 512 x 16 bit column decoder sense amplifier & i(o) bus row decoder sense amplifier & i(o) bus row decoder row decoder column decoder sense amplifier & i(o) bus row address buffer column address buffer refresh counter sense amplifier & i(o) bus a0 - a12, ba0, ba1 a0 - a8, ap, ba0, ba1 column addresses row addresses input buffer output buffer dq0 - dq15 control logic & timing generator clk cke cs ras cas we udqm ldqm column decoder column decoder
data sheet 11 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram functional description 3 functional description the 256mbit mobile-ram is a new generation of low power, four bank synchronous dram organized as 4banks 4mbit 16 with additional features for mobile applic ations. the synchronous mobile-ram achieves high speed data transfer rates by employing a chip architec ture that prefetches multiple bits and then synchronizes the output data to a system clock. the device adds new features to the industry standards set for synchronous dram products. parts of the memory array can be selected for self-refresh and the refresh period during self-refresh is programmable in 4 steps which drastically reduces the self refresh current, depending on the case temperature of the components in the system application. in addition a ?d eep power down mode? is available. operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate. a sequential and gapless data rate is possible depending on burst length, cas latency and speed grade of the device. prior to normal operation, the 256mbit mobile-ram must be initialized. the following sections provide detailed information covering device initializ ation, register definition, command descriptions and device operation. 3.1 initialization the default power on state of the mode register is su pplier specific and may be u ndefined. the following power on and initialization sequence guarante es the device is preconditioned to each users specific needs. like a conventional dram, the 256mbit mobile-ram must be pow ered up and initialized in a predefined manner. v dd must be applied before or at the same time as v ddq to the specified voltage when the input signals are held in the ?nop? or ?deselect? state. the power on voltage must not exceed v dd + 0.3 v on any of the input pins or v ddq supplies. the clk signal must be started at the sa me time. after power on, an initial pause of 200 s is required followed by a precharge of all banks using the precha rge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode re gister set command must be issued to initialize the mode register. a minimum of two auto refresh cycles (cbr) are also required. these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start-up modes. 3.2 mode register definition the mode register designates the operat ion mode at the read or write cycle. this register is divided into four fields. a burst length field to set the length of the burst , an addressing selection bit to program the column access sequence in a burst cycle (interleaved or sequential), an d a cas latency field to set the access time at clock cycle, an the mode set operation must be done before any activate command after the initial power up. any content of the mode register can be altered by re-e xecuting the mode set command. all banks must be in precharged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is required. low signals of ras , cas , and we at the positive edge of the clock activate the mode set operation. address input data at this timing defines parameters to be set as shown in the previous table. ba0 and ba1 have to be set to ?0? to enter the mode register.
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram functional description data sheet 12 rev. 1.40, 2005-08 3.2.1 burst length read and write accesses to the 256mbit mobile-ram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst le ngths of 2, 4, or 8 locations are av ailable for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of column s equal to the burst length is effectively selected. all accesses for that burst take place within this block, mean ing that the burst wraps withi n the block if a boundary is reached. the block is uniquely selected by ai-a1 when th e burst length is set to tw o, by ai-a2 when the burst length is set to four and by ai-a3 when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burs t length applies always to read bursts and depending on a9 in operating mode also on write bursts. mr mode register definition (ba[1:0] = 00 b ) ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 0 0 mode cl bt bl reg. addr w w w w field bits type description bl [2:0] w burst length number of sequential bits per dq rela ted to one read/write command; see chapter 3.2.1 . note: all other bit comb inations are reserved. 000 1 001 2 010 4 011 8 111 full page (sequential burst type only) bt 3w burst type see table 5 for internal address sequence of low order address bits; see chapter 3.2.2 . 0 sequential 1 interleaved cl [6:4] w cas latency number of full clocks from read command to first data valid window; see chapter 3.2.3 . note: all other bit comb inations are reserved. 010 2 011 3 mode [12:7] w operating mode see chapter 3.2.4 . note: all other bit comb inations are reserved. 000000 burst read/burst write 000100 burst read/single write
data sheet 13 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram functional description 3.2.2 burst type accesses within a given burst may be programmed to be eith er sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of acce sses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 5 . note: 1. for a burst length of two, ai-a1 selects the two-data-ele ment block; a0 selects the first access within the block. 2. for a burst length of four, ai-a2 selects the four-dat a-element block; a1-a0 selects the first access within the block. 3. for a burst length of eight, ai-a3 selects the eight-dat a- element block; a2-a0 selects the first access within the block. 4. whenever a boundary of the block is reached with in a given sequence above, the following access wraps within the block. 3.2.3 read latency the read latency, or cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first burst of output da ta. the latency can be programmed 2 and 3 clocks. if a read command is registered at rising clock edge n, and the latency is m clocks, the data is available nominally coincident with rising clock edge n + m . reserved states should not be used as unknown operati on or incompatibility with futu re versions may result. 3.2.4 operating mode the normal operating mode is selected by issuing a mode register set command with bits a12-a7 set to zero, and bits a6-a0 set to the desired values. burst length for write bursts is fixed to one by issuing a mode register set command with bits a12-a10 and a8-a7 each set to zero , bit a9 set to one, and bits a0-a6 set to the desired values. all other combinations of values for a12-a7 are rese rved for future use and/or test modes. test modes and reserved states should not be used as unknown operation or incompatibility wit h future versio ns may result. table 5 burst definition burst length starting column address order of accesses within a burst a2 a1 a0 type = sequential type = interleaved 200-10-1 11-0 1-0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0000-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0011-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0102-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0113-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1004-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1015-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1106-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1117-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram functional description data sheet 14 rev. 1.40, 2005-08 3.3 extended mode register the extended mode register controls functions beyond those controlled by the mode register. these additional functions are unique to mobile rams and includes a re fresh period field (tcsr) for temperature compensated self rrefresh and a partial array self refresh field (pasr). the extended mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 1) and retains the stored information un til it is programmed again or the device looses power. the extended mode register must be loaded when all banks are idle, and the c ontroller must wait the specif ied time before initiating any subsequent operation. violating either these requirem ents result in unspecified operation. unused bit a12 to a5 have to be programmed to ?0?. 3.3.1 partial arr ay self refresh the pasr field is a power saving feature specific to mob ile-rams and is used to spec ify whether only one quarter or half of bank 0, one bank (bank 0), two banks (banks 0 + 1) or all four banks (default) of the sdram array are enabled for self refresh. disabled b anks will not be refreshed in self refres h mode and writte n data will get lost after a period defined by t ref . 3.3.2 temperature compensated self re fresh with on-chip temperature sensor dram devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain the stored information. this refresh requirment heav ily depends on the die temperature: high temperature corresponds to short refresh period, and low temperature to long refresh period. the mobile-ram is equipped with an on-chip temperature sensor which continuously monitors the current die temperature and adjusts the refresh period in self refresh mode accordingly. by default the on-chip temperature sensor is enabled (tcsr = 00, see table "emr" on page 14 ); the other three tcsr settings use defined temperature values to adjust the self refresh period to with the on-chip temperat ure sensor being disabled. emr extended mode register definition (ba[1:0] = 10 b ) ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 1 0 mode tcsr pasr reg. addr w w w field bits type description 1) 1) all other bit combin ations are reserved. pasr [2:0] w partial array self refresh see chapter 3.3.1 000 banks to be self refreshed: all 4 of 4 001 banks to be self refreshed: 2 of 4, ba[1:0] = 00 b or 01 b 010 banks to be self refreshed: 1 of 4, ba[1:0] = 00 b 101 banks to be self refresh ed: 0.5 of 4, ba[1:0] = 00 b & ra12 = 0 b 110 banks to be self refreshed: 0.25 of 4, ba[1:0] = 00 b & ra[12:11] = 00 b tcsr [4:3] w temperature compensated self refresh see chapter 3.3.2 . 00 on-chip temperature sensor enabled 01 maximum case temperature: 45c, on-chip temperature sensor disabled 10 maximum case temperature: 15c, on-chip temperature sensor disabled 11 maximum case temperature: 85c, on-chip temperature sensor disabled mode [12:5] w operating mode 00h normal operation
data sheet 15 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram functional description 3.4 commands all of sdram operations are defined by states of control signals cs , ras , cas , we , and dqm at the positive edge of the clock. the following list shows the truth table for the operation commands. table 6 operation definition 1) 1) v = valid, x = don?t care, l = low level, h = high level. operation device state cke n-1 2) 2) cke n signal is input level when commands are provided, cke n-1 signal is input level one clock before the commands are provided. cke n 2) dqm ba1 ba0 ap= a10 addr cs ras cas we bank active idle 3) 3) this is the state of the ban ks designated by ba0, ba1 signals. hxx vvv ll hh bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active 3) hxx vlv lhl l write with autoprecharge active 3) hxx vhv lhl l read active 3) hxx vlv lhl h read with autoprecharge active 3) hxx vhv lhl h mode register set idle h x x v v v l l l l no operation any h x x x x x l h h h burst stop active h x x x x x l h h l device deselect any h x x x x x h x x x auto refresh idle h h x x x x l l l h self refresh entry idle h l x x x x l l l h self refresh exit idle (self refresh) l h x x x x hx x x lh h x clock suspend entry active 4) 4) power down mode can not be entered during a burst cycle. when this command is asserted during a burst cycle the device enters clock suspend mode. h l x xxx xx x x clock suspend exit active l h x xxx xx x x power down entry (precharge or active standby) idle h l x xxx hx x x active 4) lh h h power down exit any (power down) l h x x x x hx x x lh h l data write/output enable active h x l x x x x x x x data write/output disable active h x h x x x x x x x deep power down entry idle h l x x x x l h h l deep power down exit deep power down 5) 5) after deep power down mode exit a full new initialisation of the memo ry device is mandatory. l h x xxx xx x x
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram functional description data sheet 16 rev. 1.40, 2005-08 deselect the deselect function prevents new commands from be ing executed by the 256mbit mobile-ram. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to a 256mbit mobile-ram. this prevents unwanted commands from being registered during idle or wait st ates. operations already in progress are not affected. mode register set the mode registers are loaded via inputs a12-a0, ba1 and ba0. see mode register descriptions in chapter 3.2 . the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable comman d cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. this is called the start of a ras cycle and occures when ras is low and both cas and we are high at the positive edge of the clock. the value on the ba1 and ba0 inputs selects the ba nk, and the address provided on inputs a12-a0 selects the row. this row remains active (o r open) for accesses until a precharge (or read or write with auto precharge) is issued to that bank. a precharge (or read or wr ite with auto precharge) command must be issued and completed before opening a different row in the same bank. read and write a cas cycle is triggered by setting ras high and cas low at a clock timing after a necessary delay, t rcd , from the ras timing. we is used to define either a read (we = h) or a write (we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 133 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, which is one of 1, 2, 4, 8 and fu ll page. column addresses are segmented by the burst length and serial data accesses are done within this boundary. the first column address to be accessed is supplied at the cas timing and the subsequent addresses are generat ed automatically by the programmed burst length and its sequence. for example, in a burst le ngth of 8 with interleave sequence, if the first address is ?2?, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. full page burst operation is only possible using the sequent ial burst type and page length is a function of the i/o organisation and column addressing. full page burst operat ion does not self terminate once the burst length has been reached. in other words, unlike burst length of 2, 4 an d 8, full page burst continue s until it is terminated using another command. similar to the page mode of conventional dram?s, burst read or write accesses on any column address are possible once the ras cycle latche s the sense amplifiers. the maximum t ras or the refresh interval time limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycle is supported. wh en the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. an interrupt which accompanies an operation change from a read to a write is po ssible by exploiting dqm to avoid bus contention. when two or more banks are activated sequentially, interl eaved bank read or write operations are possible. with the programmed burst length, alternate access and precha rge operations on two or more banks can realize fast serial data access modes among many different pages. once two or more banks are activated, column to column interleave operation can be performed between different pag es. when the partial array activation is set, data will get lost when self-refresh is used in all non activated banks. the read command is used to initiate a burst read access to an active (open) row. the value on the ba1 and ba0 inputs selects the bank, and the address provided on inpu ts a9-a0 for x16 selects the starting column location. the value on input a10/ap determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the read bur st; if auto precharge is not selected, the row remains open for subsequent accesses.
data sheet 17 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram functional description the write command is used to initiate a burst write acce ss to an active (open) row. the value on the ba1 and ba0 inputs selects the bank, and the address provided on inpu ts a9-a0 for x16 selects the starting column location. the value on input a10/ap determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at th e end of the write burst; if auto precharge is not selected, the row remains open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a gi ven dqm signal is registered low, the corresponding data is written to memory; if the dqm signal is registered high, the corresponding data inputs are ignored, and a write is not executed to that byte/column location. precharge the precharge command is used to deactivate (close) the ope n row in a particular bank or the open row(s) in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp ) after the precharge command is issued. when ras and we are low and cas is high at a clock edge, it triggers the precharge operation. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the ban k. otherwise ba0, ba1 are treated as ?don?t care? (see table 7 ). once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging. the precharge command can be imposed one clock before the last data out for cas latency = 2 and two clocks before the last data out for cas latency = 3. writes require a time delay t wr from the last data out to apply the precharge command. auto precharge auto precharge is a feature which performs the same in dividual-bank precharge func tions described above, but without requiring an explicit command . this is accomplished by using a10/ap to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/ row that is addressed with the read or write command is automatically perf ormed upon completion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge ( t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time. the 256mbit mobile-ram automatically enters the precharge operation after t wr (write recovery time) fo llowing the last data in. burst terminate once a burst read or write operation has been initiated, there are several methods used to terminate the burst operation prematurely. these methods include using ano ther read or write command to interrupt an existing burst operation, usi ng a precharge command to interr upt a burst cycle and close the active bank, or using the burst stop command to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid dq contention. the bu rst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presen ted on the dq pins before th e burst stop command is regist ered will be written to the memory. table 7 bank selection by address bits with precharge a10 ba0 ba1 000bank 0 001bank 1 010bank 2 011bank 3 1xxall banks
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram functional description data sheet 18 rev. 1.40, 2005-08 auto refresh auto refresh is used during normal operation of the 25 6mbit mobile-ram and is analogous to cas before ras (cbr) refresh in previous dram types. this command is nonpersistent, so it must be issued each time a refresh is required. all banks must be precharged before ap plying any refresh mode. an on-chip address counter increments the word and the bank addresses. this makes the address bits ?don?t care? during an auto refresh command. the chip enters the auto refresh mode, when ras and cas are held low and cke and we are held high at a clock edge. the mode restores word line after the refr esh and no external precharge command is necessary. a minimum t rc time is required between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. in auto-refresh mode all banks are refreshed, independendly of the fact that the partial array self-refresh has been set or not. self refresh the chip has an on-chip timer that is used when the self refresh mode is entered. the self-refresh command is asserted with ras , cas , and cke low and we high at a clock edge. all external control signals including the clock are disabled. returning cke to high enables the clock and initiates the refresh exit operation. after the exit command, at least one t rc delay is required prior to any access command. the use of self refresh mode introduces the possibility that an iternally timed event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh an extra auto refresh command is recommended. low power sdrams have the possibilit y to program the refresh period of the on-chip timer with the use of an appropriate extended mrs command, depending on the maxi mum operation case temperature in the application. in partial array self re fresh mode only the selected banks will be refres hed. data written to the non activated banks will get lost after a pe riod defined by tref. dqm function dqm has two functions for data i/o read and write operations. during reads, when it turns to ?high? at a clock edge, data outputs are disabled and become high impedanc e after two clock periods (dqm data disable latency t dqz ). it also provides a data mask function for writes. when dq m is activated, the write op eration at the next clock is prohibited (dqm write mask latency t dqw = zero clocks). suspend mode during normal access, cke is held high enabling the clock. when cke is low, it freezes the internal clock and extends data read and write operations . one clock delay is required for mode entry and exit (clock suspend latency t csl ). power down in order to reduce standby power consumption, a power down mode is available. all banks must be precharged before the mobile-ram can enter the power down mode. on ce the power down mode is initiated by holding cke low, all receiver circuits except for clk and cke are gated off. the power down mode does not perform any refresh operations, therefore the devic e can?t remain in power down mode longer than the refresh period ( t ref ) of the device. exit from this mode is performed by ta king cke ?high?. one clock delay is required for power down mode entry and exit. deep power down mode the deep power down mode is an unique function on mobile rams with very low standby currents. all internal voltage gene rators inside the mobile rams are stopped an d all memory data is lost in this mode. to enter the deep power down mode all banks must be precharged.
data sheet 19 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram functional description 3.5 simplified state diagram figure 3 simplified state diagram power on mode register set power applied deep power down dpdsx mrs act self refresh refs refsx idle dpds auto refresh refa active power down ckeh ckel row active w r i t e read write a read a precharge read reada writea reada writea pre read a pre automatic sequence command sequence clock suspend read clock suspend reada clock suspend write clock suspend writea r e a d b s t b s t ckel ckel ckel ckel ckeh ckeh ckeh ckeh preall = precharge all banks refs = enter self refresh refsx = exit self refresh refa = auto refresh dpds = enter deep power down dpdsx = exit deep power down ckel = enter power down ckeh = exit power down read = read w/o auto precharge reada = read with auto precharge write = write w/o auto precharge writea = write with auto precharge precharge all preall ckel ckeh precharge power down write writea write pre pre act = active pre = precharge bst = burst terminate mrs = mode register set
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram electrical characteristics data sheet 20 rev. 1.40, 2005-08 4 electrical characteristics 4.1 operating conditions attention: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. table 8 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?1.0 ? v dd +0.5 v ? voltage on i/o pins relative to v ss v in , v out ?1.0 ? +4.6 v ? voltage on v dd supply relative to v ss v dd ?1.0 ? +4.6 v ? voltage on v ddq supply relative to v ss v ddq ?1.0 ? +4.6 v ? operating case temperature (extended) t case ?25 ? +85 c? storage temperature (plastic) t stg ?55 ? +150 c? power dissipation p d ??0.7w? short circuit output current i out ?50?ma? table 9 recommended operating conditions and dc characteristics 1) 1) 0 c t c 70 c (comm.) and ?25 c t case +85 c parameter symbol values unit note/ test condition min. max. supply voltage v dd +2.3 +3.6 v ? i/o supply voltage v ddq +1.65 +3.6 v 2) 2) v ddq < v dd + 0.3 v supply voltage v ss 00 v? i/o supply voltage v ssq 00 v? input high (logic 1) voltage v ih 0.8 x v ddq v ddq + 0.3 v 3)4) 3) all voltages referenced to v ss 4) v ih may overshoot to v ddq + 2.0 v for pulse width of < 4 ns. v il may undershoot to ? 2.0 v for pulse width < 4 ns. pulse width measured at 50% points with amplitude measured peak to dc reference input low (logic 0) voltage v il ?0.3 +0.3 v 3)4) output high (logic 1) voltage v oh v ddq ? 0.2 ? v i oh = ?0.1 ma output low (logic 0) voltage v ol ?+0.2vi oh = +0.1 ma input leakage current i il ?5 +5 a any input 0 v v in v dd ; all other pins not under test v in =0v output leakage current i oz ?5 +5 a dq is disabled; 0 v v out v ddq
data sheet 21 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram electrical characteristics 4.2 timing characteristics table 10 input and output capacitances parameter symbol values unit note/ test condition min. typ. max. input capacitance: clk c i1 ??3.5pf 1) 1) these values are guaranteed by design and are tested on a sample base only. v ddq = v dd = 2.5 v 0.2 v, f = 1 mhz, t case =25 c, v out(dc) = v ddq /2, v out (peak to peak) 0.2 v. unused pins are tied to ground. input capacitance: all other input-only pins c i2 ??3.8pf 1) input/output capacitance: dq c io 4.0 ? 5.0 pf 1) table 11 ac timing characteristics 1)2) parameter symbol ?7.5 unit note/ test condition min. max. clock dq output access time from clk t ac3 ?7.5 ns v ddq <2.3v 3)4)5)8) ?6 ns v ddq 2.3 v 3)4)5)8) ? 5.4 ns v ddq 3.0 v 3)4)5)8) t ac2 ?7.5 ns v ddq <2.3v 3)4)5)8) ?6 ns v ddq 2.3 v 3)4)5)8) ck high-level width t ch 2.5 ? ns ? ck low-level width t cl 2.5 ? ns ? clock cycle time t ck3 7.5 ? ns v ddq 2.3 v 3) 8? ns v ddq <2.3v 3) t ck2 9.5 ? ns 3) clock frequency f ck3 ?133mhz v ddq 2.3 v 3) ?125mhz v ddq <2.3v 3) f ck2 ?105mhz 3) setup and hold times input setup time t is 1.5 ? ns 6) input hold time t ih 0.8 ? ns 6) cke setup time t cks 1.5 ? ns 6) cke hold time t ckh 0.8 ? ns 6) mode register setup time t rsc 2? t ck ? power down moder entry time t sb 07.5 ns? common parameters active to read or write delay t rcd 19 ? ns 7) precharge command period t rp 19 ? ns 7) active to precharge command t ras 45 100000 ns 7) active bank a to active bank a period t rc 67 ? ns 7) active bank a to active bank b delay t rrd 15 ? ns 7) cas to cas command delay t ccd 1? t ck ?
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram electrical characteristics data sheet 22 rev. 1.40, 2005-08 figure 4 measurement conditions for t ac and t oh refresh cycle refresh period t ref ?64 ms? self refresh exit time t srex 1? t ck ? read cycle data output hold time t oh 3? ns 4)7)8) data output from high to low impedance t lz 1? ns? data output from low to high impedance t hz 37 ns? dqm data output disable latency t dqz ?2 t ck ? write cycle write recovery time t wr 14 ? ns 9) dqm write data mask latency t dqw 0? t ck ? 1) 0 c t c 70 c (comm.) and ?25 c t case +85 c; recommended operating conditions unless otherwise noted 2) for proper power-up see the opera tion section of this data sheet. 3) symbol index 2 and 3 refer to cl = 2 and cl = 3. 4) ac timing tests are referenced to the 0.9 v crosso ver point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit (details will be defined later). specified t ac and t oh parameters are measured with a 30 pf on ly, without any resistive termination and with a input signal of 1v/ns edge rate (see figure 4 ). 5) if clock rising time is longer than 1 ns, a time ( t t /2 - 0.5) ns has to be added to this parameter. 6) if t t is longer than 1 ns, a time ( t t - 1) ns has to be added to this parameter. 7) these parameter account for the number of clock cycle and de pend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timi ng period (counted in fractions as a whole number) 8) access time from clock t ac is 4.6 ns for ?7.5 components with no termination and 0 pf load, data out hold time t oh is 1.8 ns for ?7.5 components with no termination and 0 pf load. 9) the write recovery time of t wr = 14 ns allows the use of one clock cycle for the write recovery time when the memory operation frequency is equal or less than 72mhz. for all me mory operation frequencies higher than 72mhz two clock cycles for t wr are mandatory. infineon recommends to use two clock cy lces for the write recovery time in all applications. table 11 ac timing characteristics 1)2) (cont?d) parameter symbol ?7.5 unit note/ test condition min. max. 30 pf i/o
data sheet 23 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram electrical characteristics 4.3 current specification table 12 i dd specification and conditions 1)2) 1) 0 c t c 70 c (comm.) and ?25 c t case +85 c; recommended operating conditions unless otherwise noted 2) for proper power-up see the opera tion section of this data sheet. parameter symbol ?7.5 unit note/ test condition typ. max. operating current single bank access cycles i dd1 ?65 ma t rc = t rc,min 3) 3) these parameters depend on the frequency. these values are measured at 133mhz for ?7.5 and at 100mhz for ?8 parts. input signals are changed once during t ck . if the devices are operating at a fr equency less than the maximum operation frequency, these current values are reduced. precharge standby current power down mode i dd2p ?0.6 macs = v ih,min , cke v il,max 3) precharge standby current non power down mode i dd2n ?20 macs = v ih,min , cke v ih,min 3) non operating current active state of 1 upto 4 banks, power down i dd3p ?3.5 macs = v ih,min , cke v il,max 3) non operating current active state of 1 upto 4 banks, non power down i dd3n ?25 macs = v ih,min , cke v ih,min 3) burst operating current read command cycling i dd4 ?80 ma 3)4) 4) these parameters are measured with continuous data stre am during read access and all dqs toggling. cl = 3 and bl = 4 is used and the v ddq current is excluded. auto refresh current auto refresh command cycling i dd5 ? 155 ma t rc = t rc,min self refresh current i dd6 see table 13 a t ck =infinity, cke = 0.2 v deep power down mode current i dd7 ?5 a
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram electrical characteristics data sheet 24 rev. 1.40, 2005-08 table 13 i dd6 programmable self refresh current 1)2) 1) recommended operating condi tions unless otherwise noted 2) for proper power-up see the opera tion section of this data sheet. parameter symbol ?8 unit t case note/ test condition max. tcsr 3) 3) extended mode register a4-a3, see ?temperature compensated self refresh with on-chip temperature sensor? on page 14 self refresh current self refresh mode, full array activations = all banks i dd6 t.b.d. amax. 15c t ck =infinity, cke = 0.2 v 4) 4) target values to be verified on final product and may change. 250 amax. 45c 475 amax. 70c 725 a max. 85c self refresh current self refresh mode, half array activations = bank 0 + 1 i dd6 t.b.d. amax. 15c t ck =infinity, cke = 0.2 v 4) 150 amax. 45c 250 amax. 70c 450 a max. 85c self refresh current self refresh mode, quarter array activations = bank 0 i dd6 t.b.d. amax. 15c t ck =infinity, cke = 0.2 v 4) 100 amax. 45c 150 amax. 70c 275 a max. 85c
data sheet 25 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams 5 timing diagrams figure 5 bank activate command cycle figure 6 burst read operation figure 7 read interrupted by a read read to write interval ? figure 8 read to write interval ? figure 9 minimum read to write interval ? figure 10 non-minimum read to write interval figure 11 burst write operation write and read interrupt ? figure 12 write interrup ted by a write ? figure 13 write interrupted by read burst write & read with auto-precharge ? figure 14 burst write with auto-precharge ? figure 15 burst read with auto-precharge ac- parameters ? figure 16 ac parameters for a write timing ? figure 17 ac parameters for a read timing figure 18 mode register set figure 19 power on sequence and auto refresh (cbr) clock suspension (using cke) ? figure 20 clock suspension during burst read cas latency = 2 ? figure 21 clock suspension during burst read cas latency = 3 ? figure 22 clock suspension during burst write cas latency = 2 ? figure 23 clock suspension during burst write cas latency = 3 figure 24 power down mode and clock suspend figure 25 self refresh (entry and exit) figure 26 auto refresh (cbr) random column read ( page within same bank) ? figure 27 cas latency = 2 ? figure 28 cas latency = 3 random column write ( page within same bank) ? figure 29 cas latency = 2 ? figure 30 cas latency = 3 random row read (interleaving banks) with precharge ? figure 31 cas latency = 2 ? figure 32 cas latency = 3 random row write (interleaving banks) with precharge ? figure 33 cas latency = 2 ? figure 34 cas latency = 3 precharge termination of a burst ? figure 35 cas latency = 2 deep power down mode ? figure 36 deep power down mode entry ? figure 37 deep power down mode exit
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 26 rev. 1.40, 2005-08 figure 5 bank activate command cycle figure 6 burst read operation rc "h" or "l" t t0 (cas latency = 3) bank b row addr. activate bank b address command clk t nop nop rcd t t1 col. addr. bank b with auto precharge write b t spt03784 bank b row addr. activate bank b row addr. bank a activate bank a t nop rrd t tt spt03712 clk read a nop t0 t1 t2 t3 t4 t5 t6 t7 t8 command nop nop nop nop nop nop nop dout a3 ck2 latency = 2 t , dq?s dout a1 dout a0 dout a2 dout a2 ck3 latency = 3 t , dq?s dout a0 dout a1 dout a3 (burst length = 4, cas latency = 2, 3) cas cas
data sheet 27 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams figure 7 read interrupted by a read read to write interval figure 8 read to write interval spt03713 clk read a t0 t1 t2 t3 t4 t5 t6 t7 t8 command dout a0 dout b0 dout b1 dout b2 nop nop nop nop nop nop nop latency = 2 , dq?s ck2 t ck3 latency = 3 t , dq?s (burst length = 4, cas latency = 2, 3) cas cas read b dout b3 dout b1 dout a0 dout b0 dout b3 dout b2 commands = 4 + 1 = 5 cycles minimum delay between the read and write dout a0 dq?s (burst length = 4, cas latency = 3) dqmx command clk nop read a t0 t1 nop nop t2 t3 the write command must be hi-z before din b0 din b1 spt03787 din b2 dqw nop dqz t nop t t4 t5 write b nop t6 t7 nop t8 "h" or "l" write latency of dqmx
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 28 rev. 1.40, 2005-08 figure 9 minimum read to write interval the write command must be hi-z before activate cas ck2 latency = 2 t , dq?s (burst length = 4, cas latency = 2) clk dqm command nop t0 t1 bank a nop dqz t t2 t3 din a0 din a1 din a2 spt03939 din a3 1 clk interval read a write a t4 t5 nop nop t6 t7 nop t8 "h" or "l" t dqw nop
data sheet 29 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams figure 10 non-minimum read to write interval figure 11 burst write operation cas latency = 3 ck3 cas ck2 latency = 2 t t , dq?s , dq?s dout a0 (burst length = 4, cas latency = 2, 3) clk dqm command nop read a t0 t1 nop nop t2 t3 the write command must be hi-z before dout a0 dout a1 din b0 din b0 din b1 din b1 spt03940 din b2 din b2 read a dqz t nop t4 t5 write b nop t6 t7 nop t8 "h" or "l" t dqw extra data is ignored after termination of a burst. din a3 t4 are registered on the same clock edge. the first data element and the write nop (burst length = 4, cas latency = 2, 3) t0 command dq?s clk din a1 t2 nop din a0 write a t1 din a2 nop t3 spt03790 t6 nop nop t5 nop nop t7 nop t8 don?t care
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 30 rev. 1.40, 2005-08 write and read interrupt figure 12 write interrupted by a write figure 13 write interrupted by a read spt03791 clk t0 t1 t2 t3 t4 t5 t6 t7 t8 command nop nop nop nop nop nop dq?s (burst length = 4, cas latency = 2, 3) nop write a din a0 din b0 din b1 din b2 din b3 write b 1 clk interval t5 nop dout b1 dout b0 input data for the write is ignored. , dq?s latency = 3 ck3 cas t don?t care din a0 don?t care (burst length = 4, cas latency = 2, 3) clk , dq?s command latency = 2 ck2 cas t nop t0 din a0 write a don?t care read b t1 t2 dout b0 nop nop t4 t3 spt03719 appears on the outputs to avoid data contention. dout b2 input data must be removed from the dq?s at least one clock cycle before the read data dout b1 dout b3 nop dout b3 nop dout b2 t6 t7 nop t8
data sheet 31 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams burst write and read with auto precharge figure 14 burst write with auto-precharge figure 15 burst read with auto-precharge spt03909_2 clk active nop t0 t1 t2 t3 t4 t5 t6 t7 t8 command nop nop nop nop dq's bank a begin auto precharge bank can be reactivated after trp write a auto precharge din a1 din a0 din a1 din a0 cas latency = 2: dq's cas latency = 3: wr t wr t rp t rp t * * * active nop command nop nop nop nop nop nop bank a w rite a auto precharge nop a ctivate (burst length = 2, cas latency = 2, 3 ) activate spt03721_2 clk with ap nop t0 t1 t2 t3 t4 t5 t6 t7 t8 command dout a0 dout a1 dout a2 dout a3 nop nop nop nop nop nop nop latency = 2 dq's dout a3 latency = 3 dout a1 dout a0 dout a2 (burst length = 4, cas latency = 2, 3) cas cas read a bank can be reactivated after trp begin auto precharge dq's rp t * * * t rp
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 32 rev. 1.40, 2005-08 ac parameters figure 16 ac parameters for a write timing auto precharge bank b command write with activate write with activate bank a command auto precharge bank a command command bank b addr. ap dqm dq bs hi-z rcd t ax2 ax1 ax0 ax3 rc t rax t as t ah rbx cax command spt03910_2 bx1 bx0 cbx t8 precharge begin auto bank a clk we cas ras cs cke ck2 t cs t ch cks t ch t t cl t t3 t0 t2 t1 t4 t5 t7 t6 t18 burst length = 4, cas latency = 2 t13 t9 t10 t12 t11 t14 t15 t17 t16 t19 t20 t22 t21 rbx rax activate w rite command bank a bank a ds t t dh ray bank b precharge begin auto rby activate precharge command bank a bank a command activate bank b command t wr t ckh raz raz rby ray ray bx2 bx3 t wr rp t ay2 ay1 ay0 ay3 rp t rrd t
data sheet 33 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams figure 17 ac parameters for a read timing ac2 hi-z dq activate command bank a read bank a command dqm addr. ap t rcd t lz t t as rax rax t ah cax rrd t command bank b read with auto precharge activate bank b command ax1 ax0 bx0 activate spt03911_2 command bank a bx1 t ac2 oh t hz t t ras rc t rbx rbx rbx hz t ray ray t5 t t bs we cas ras t cs cke cks t ch t t cs ch cl ck2 clk t0 t1 t2 t3 t4 precharge bank b begin auto t ckh burst length = 2, cas latency = 2 t6 t7 t8 t10 t9 t11 t13 t12 rp t precharge bank a command
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 34 rev. 1.40, 2005-08 figure 18 mode register set set command mode register a ll b anks precharge command any command address key t0 t1 t2 t8 rsc t t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 spt03912_2 t19 t16 t15 t14 t17 t18 cas latency = 2 t20 t21 t22 bs addr. ap cs we cas ras cke clk
data sheet 35 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams figure 19 power on sequence and auto refresh (cbr) inputs must be 200 stable for s dqm ap dq addr. bs rp command all banks precharge hi-z ~ ~ t 1st auto refresh command ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ spt03913 mode register set command address key 8th auto refresh command ~ ~ t rc ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ command any minimum of 8 refresh cycles are required t8 we cas ras cs cke clk required ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t3 is ~ ~ ~ ~ level high t0 t2 t1 t5 t4 t7 t6 t18 2 clock min. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t13 ~ ~ ~ ~ t10 t9 t12 t11 t14 t15 t17 t16 t20 t19 t22 t21
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 36 rev. 1.40, 2005-08 clock suspension (using cke) figure 20 clock suspension during burst read cas latency = 2 command bank a dqm addr. dq ap bs read command bank a activate hi-z suspend 1 cycle clock ax0 csl t ax1 cax rax rax spt03914 t suspend 3 cycles suspend 2 cycles clock ax2 csl t clock ax3 hz t7 we cas ras cs cke clk ck2 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 t18 t17 t19 t20 t21 t22 csl t
data sheet 37 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams figure 21 clock suspension during burst read cas latency = 3 csl dqm addr. dq ap bs bank a activate command hi-z command bank a read ax0 t rax rax cax hz t t suspend 1 cycle clock suspend 2 cycles clock csl ax1 ax2 clock suspend 3 cycles t csl ax3 spt03915 t7 we cas ras cs cke clk ck3 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 3 t18 t17 t19 t20 t21 t22
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 38 rev. 1.40, 2005-08 figure 22 clock suspension during burst write cas latency = 2 bank a dqm addr. dq ap bs dax0 command write activate command bank a hi-z clock clock 1 cycle suspend suspend 2 cycles dax1 cax rax rax dax3 clock suspend 3 cycles dax2 spt03916 t7 we cas ras cs cke clk ck2 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 t18 t17 t19 t20 t21 t22
data sheet 39 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams figure 23 clock suspension during burst write cas latency = 3 clock suspend 2 cycles bank a dqmx addr. dq a8/ap ba activate command bank a hi-z clock 1 cycle suspend command write dax0 dax1 rax rax cax clock suspend 3 cycles dax2 dax3 spt03917 t7 we cas ras cs cke clk ck3 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 3 t18 t17 t19 t20 t21 t22
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 40 rev. 1.40, 2005-08 figure 24 power down mode and clock suspend bs clock suspend clock suspend mode entry mode exit addr. dqm dq ap standby active activate bank a command hi-z read command bank a rax rax cax power down power down mode exit mode entry spt03918 end clock mask clock mask start ax0 ax1 ax2 precharge command bank a ax3 t hz precharge standby any command t7 cas we ras cs cke clk ck2 t t0 t1 t2 cks t t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 cks t t18 t17 t19 t20 t21 t22
data sheet 41 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams figure 25 self refresh (entry and exit) bs t addr. dqm dq ap hi-z spt03919-4 srex t rc any command t7 cs cas we ras cke clk t0 t1 t2 t3 t4 t6 t5 t16 cks t t8 t9 t10 t11 t14 t12 t13 t15 t18 t17 t19 t20 t21 t22 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ entry self refresh exit command begin self refresh self refresh exit command issued (async.) must be idle all banks t cks
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 42 rev. 1.40, 2005-08 figure 26 auto refresh (cbr) (m inim um interval) addr. dqm dq ap bs auto refresh command all banks precharge command hi-z t rp t rc spt03920_2 rc t rax rax cax t7 we cas ras cs cke clk ck2 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 4, cas latency = 2 t18 t17 t19 t20 t21 t22 command auto refresh command command bank a activate bank a read ax2 ax0 ax1 ax3
data sheet 43 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams random column read (page within same bank) figure 27 cas latency = 2 ay1 addr. bs dq dqm ap activate command z hi bank a raw raw command read command bank a read bank a aw0 aw1 caw cax read bank a command aw3 aw2 ax0 ax1 ay0 cay cs we cas ras cke clk t0 ck2 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 precharge command bank a ay2 ay3 activate command bank a raz raz spt03921 read bank a command caz burst length = 4, cas latency = 2 t19 t16 t15 t14 t17 t18 t20 t21 t22 az3 az0 az1 az2
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 44 rev. 1.40, 2005-08 figure 28 cas latency = 3 ay3 caw addr. bs dq dqm ap z hi bank a activate command read command bank a raw raw bank a command aw1 aw0 read bank a command aw2 aw3 cax read ax1 ax0 ay0 precharge command bank a ay1 ay2 cay cs we cas ras cke clk t0 ck3 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 bank a read command activate command bank a raz raz caz spt03922 burst length = 4, cas latency = 3 t19 t16 t15 t14 t17 t18 t20 t21 t22
data sheet 45 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams random column write (page within same bank) figure 29 cas latency = 2 dby1 addr. bs dq dqm ap activate command z hi bank b rbw rbw command write command bank b write bank b dbw0 dbw1 cbw cbx write bank b command dbw3 dbw2 dbx0 dbx1 dby0 cby cs we cas ras cke clk t0 ck2 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 precharge command bank b dby2 dby3 activate command bank b rbz rbz spt03923_2 read bank b command cbz burst length = 4, cas latency = 2 t19 t16 t15 t14 t17 t18 t20 t21 t22 dbz1 dbz0 dbz2 dbz3
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 46 rev. 1.40, 2005-08 figure 30 cas latency = 3 command write bank b cbz dbw0 addr. bs dq dqm ap bank b activate command z hi rbz rbz command bank b dbw3 dbw1 dbw2 write bank b command dbx0 dbx1 cbx write dby1 dby0 dby2 precharge command bank b dby3 cby cs we cas ras cke clk t0 ck3 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 command bank b dbz0 activate command bank b write dbz1 rbz rbz cbz spt03924 burst length = 4, cas latency = 3 t19 t16 t15 t14 t17 t18 t20 t21 t22
data sheet 47 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams random row read (interleaving banks) with precharge figure 31 cas latency = 2 ax2 t bs addr. dq dqm ap bank b activate command hi-z command read bank b rbx rbx rcd t cbx read activate bank a command command bank b command bx2 bx0 ac2 bx1 bank a activate bx3 bx4 rax rax command precharge bank b bx6 bx5 bx7 ax0 ax1 cax rby rby cs we cas ras cke clk t0 high t ck2 t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 spt03925_2 bank b command ax5 ax3 ax4 read ax6 ax7 cby by1 by0 burst length = 8, cas latency = 2 t19 t16 t15 t14 t17 t18 t20 t21 t22 rp t
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 48 rev. 1.40, 2005-08 figure 32 cas latency = 3 activate command bank a addr. dqm dq ap bs read bank b command command bank b activate hi-z bx1 bx0 cbx rbx rcd t rbx t ac3 activate command bank b bx6 bank a command read bx4 bx3 bx2 bx5 bank b precharge command ax0 bx7 ax2 ax1 rax cax rax rp t rby rby precharge bank a command ax7 read bank b command ax5 ax4 ax3 ax6 spt03926 by0 cby t7 we cas ras cs cke clk high ck3 t t0 t1 t2 t3 t4 t6 t5 t16 t8 t9 t10 t11 t14 t12 t13 t15 burst length = 8, cas latency = 3 t18 t17 t19 t20 t21 t22
data sheet 49 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams random row write (interleaving banks) with precharge figure 33 cas latency = 2 dbx4 dax1 bs ap addr. dq dqm activate command bank a hi-z write command bank a dax0 rax rax rcd t cax command command bank b bank a command dax4 dax2 dax3 bank b activate dax5 dax6 rbx rbx command precharge bank a write dbx0 dax7 dbx1 activate dbx2 dbx3 cbx ray ray clk cke cs ras cas we t0 high ck2 t t1 t2 t8 t4 t3 t5 t6 t7 t11 t9 t10 t12 t13 command bank a spt03927_2 command precharge bank b dbx7 dbx5 dbx6 write day0 day1 cay wr t day4 day3 day2 t19 burst length = 8, cas latency = 2 t16 t15 t14 t17 t18 t20 t21 t22 wr t rp t
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 50 rev. 1.40, 2005-08 figure 34 cas latency = 3 dax4 addr. dqm dq ap bs command bank a bank a activate command hi-z write dax0 dax1 dax3 dax2 rax rcd t rax cax dbx4 dbx0 write command bank b bank b activate command dax6 dax5 dax7 precharge command bank a dbx2 dbx1 dbx3 cbx rbx rbx wr t rp t command bank a activate command bank a write dbx5 dbx6 day0 dbx7 precharge bank b command spt03928 day1 day2 day3 wr ray t cay ray cas ras cke clk we cs t2 high ck3 t t0 t1 t4 t3 t5 t6 t15 t7 t8 t9 t10 t11 t12 t13 t14 burst length = 8, cas latency = 3 t19 t17 t16 t18 t21 t20 t22
data sheet 51 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams precharge termination of a burst figure 35 cas latency = 2 command activate bank a t14 bs write data is masked. of a write burst. precharge termination addr. dq dqm ap command bank a activate hi z bank a write command dax0 dax1 rax rax cax command bank a command precharge bank a dax3 dax2 activate ray rp t ray ay0 command bank a read bank a precharge command ay1 ay2 cay rp t t3 cs we cas ras cke clk t0 high ck2 t t1 t2 t4 t5 t7 t6 t8 t10 t9 t11 t13 t12 precharge termination of a read burst. spt03933 bank a command precharge command bank a read az0 az1 raz caz raz az2 rp t burst length = 8 or full page, cas latency = 2 t20 t17 t15 t16 t18 t19 t21 t22
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams data sheet 52 rev. 1.40, 2005-08 deep power down mode figure 36 deep power down mode entry note: the deep power down mode has to be maintained for a minimum of 100s. clk cke cs we cas ras addr. dqm dq input dq output high-z t rp precharge command deep power down entry deep power down mode dp1.vsd normal mode
data sheet 53 rev. 1.40, 2005-08 hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram timing diagrams figure 37 deep power down exit note: the deep power down mode is exited by asserting c ke high. after the exit, the following sequence is needed to enter a new command: 1. maintain nop inpu t conditions for a minimum of 200 s 2. issue precharge commands for all banks of the device 3. issue eight or more autorefresh commands 4. issue a mode register set command to initialize the mode register 5. issue an extended mode register set comm and to initialize the extende mode register clk ck e cs ra s ca s we trp all banks 200 s au to deep power do wn auto trc mode exi t prec harge refresh refresh register set exte nded mode regis ter set new com mand accepted here
hy[b/e]25l256160a[f/c]?7.5 256mbit mobile-ram package outline data sheet 54 rev. 1.40, 2005-08 6 package outline figure 38 package outline p-tfbga-54 (plastic thin small ou tline package type ii) tolerance 0.1mm for length and width smd = surface mounted device you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
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